Vhdl : very high speed integrated circuit hardware description language 超高速集成电路硬件描述语言
Vhsic - very high speed integrated circuit 超高速集成电路
Very high speed integrated circuit 超高速集成电路
As a research trial for this thesis , we designed a real circuit based on cpld ( complex programmable logic device ) by vhdl ( very high speed integrated circuit hardware description l anguage ) for the hardware algorithm for euclidean distance transform with multilayer design method , called top - to - down 一down )的方法,设计了一个基于复杂可编程逻辑器件cpld ( co哪lexprogammablelogiedeviee )的基本电路,用以验证基于硬件的欧几里德距离转换算法的各项性能。
After that , the hardware circuit , especially some of the key parts , is investigated in detail . the following processes are also investigated in detail : empoldering the four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data with vhdl ( very high speed integrated circuit hardware description language ) ; empoldering the serial interface and the data collection software in pc with borland c + + builder 接下来详细介绍了使用vhdl语言开发fpga芯片的细分、辨向、计数、锁存以及串行传输处理等全部功能;用borlandc + + builder开发了pc机上的串行接口、数据采集软件;设计并制作了fpga芯片及其外围电路的电路板。